Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

Burg, Andreas

Springer International Publishing AG

07/2017

146

Dura

Inglês

9783319604015

15 a 20 dias

Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Motivation.- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs).- GC-eDRAMs Operated at Scaled Supply Voltages.- Near-VT GC-eDRAM Implementations with Extended Retention Times.- Aggressive Technology and Voltage Scaling (to Sub-VT Domain).- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications.- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes.- Multilevel GC-eDRAM (MLGC-eDRAM).- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction.- Conclusions.
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